The present invention relates to an improvement in a phase-locked loop (PLL) circuit for regenerating a synchronizing signal necessary for demodulation of a read signal of a magnetic disc device or the like in a data processing system.
During magnetic recording of digital data in a magnetic disc device or the like, a synchronous field is detected according to a hard format system of mechanical slits, etc., or according to a soft format system of bit patterns of read data.
In the latter system, recorded data is detected as an analog signal and amplified by a magnetic head. The amplified analog waveform is converted to digital signals and then demodulated. Sampling data "1" and "0" are read out by synchronizing clock signals extracted from the data. In this case, a PLL circuit is ordinarily used to form synchronizing signals from the converted digital signals.
In the input data in the PLL circuit of the magnetic disc, before or after each data, a series of, for example, 48 bits of "0", is recorded in the front portion of data subsequent to a front gap field GAP. This series of bits "0" contains no information bits. In actuality, this field is a synchronous field SYN including synchronizing bits without data bits. The subsequent data field of read data RDATA includes synchronizing bits and data bits. Accordingly, if the PLL circuit is actuated and drawn into a synchronizing lock by the SYN field preceding the RDATA, the PLL circuit is locked and synchronous retention is maintained with the same repeated frequency by the RDATA comprising the subsequent synchronizing bits and intermediate data bits. Therefore, while the RDATA is continued, clock signals synchronous with the synchronizing bits and the data bits are always obtained from the output of the PLL circuit. When the maximum amount of data bits is intermediately inserted, the RDATA has a frequency two times as high as that of the SYN field.
Even when the phase of the data bits in the RDATA to be input to the PLL circuit is confused, synchronizing clock signals are generated without fail if the data bits fall within the lock range of the PLL circuit. The repeated frequency of input pulses to the PLL circuit is formed by synchronizing bits and data bits varying according to the content of the information. Therefore, this frequency is not constant but involves an uncertain vacant portion. In this vacant portion, the preceding comparison voltage supplied by the voltage control oscillator VCO for performing a comparison of the phases, is retained and oscillation is maintained with a frequency corresponding to the comparison voltage.
When the magnetic head starts the read operation, no synchronizing signal is obtained. Accordingly, the read operation is started at an optical position of input data. Therefore, the PLL circuit in a soft format system should be provided with a fuction for detecting the SYN and starting the synchronizing operation.
The PLL circuit according to the soft format system can be effectively used when the normal synchronizing operation is performed in the SYN field in a state where the frequency and phase of the synchronizing bits are stable this normal synchronizing operation is determined by the synchronizing bits and the data bits in the subsequent DATA portion.
However, when variations are caused in the frequency and phase, for example, by changes of the rotation speed of the magnetic recording member during reading of the field, so-called abnormal locking, that is, synchronization with a signal having a frequency other than the desired frequency, is caused. This is a defect of the conventional PLL circuit.